Analysing Single Precision Floating Point Multiplier on Virtex 2P Hardware Module

FPGAs are increasingly being used in the high performance and scientific computing community to implement floating-point based hardware accelerators. We present FPGA floating-point multiplication. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the reprogramability and parallelism of the FPGA device but also require a general purpose multiplier unit. While previous work has considered circuits for low precision floatingpoint formats, we consider the implementation of 32-bit Single precision circuits that also provide rounding and exception handling. We introduce an algorithm for multiplication and analyze its performance on Virtex2P hardware module at speed grade -7.